The present invention relates to a semiconductor photodetector, and more specifically, it relates to an avalanche multiplication photodiode having a buried structure.
In photodetectors for long-distance light communications system, the most promising type is the avalanche photodiode (APD) comprising an InGaAs/InP system.
The maximum utilization of the optical transmission characteristics of a quartz fiber light guide requires the use of light in the 1 .mu.m band, especially light of a wave length of 1.3 .mu.m or 1.6 .mu.m. By using light of the above wave length, a light communications system is capable of transmission with a bit-rate more than a few hundred megabits per second over a transmission span of a few tens of kilometers without a repeater. For such a long transmission span, an APD is indispensable because of its high response speed and high gain based on the avalanche multiplication of photo-induced carriers.
In a short span light communication system for the 1 .mu.m band, the Ge-APD is already in practical use, however, its relatively low S/N ratio characteristic limits its use for transmission over a long span. On the other hand, the APD comprising the InGaAs/InP system features lower noise and higher response speed compared with Ge-APD, especially at a 1.6 .mu.m, wavelength thanks to the relatively larger ionization rate ratio in InP, and is expected to be more suitable for applications in the aove mentioned long-span light communications.
An exemplary configuration of an InGaAs/ InP APD is illustrated in cross-section in FIG. 1. Referring to FIG. 1, stacked layers of an n-type InGaAs layer 2 (the notation of tye type is simply represented by n-, for example, hereinafer) and an n-InP layer 3 are formed on an InP substrate 1. The n-InGaAs layer 2 is for absorbing light in the 1 .mu.m band and the n-InP layer 3 having a mesa structure 31 is for constituting an avalanche multiplication region (simply referred to as multiplication region hereinafter), as shown in FIG. 1. Between the n-InGaAs layer 2 and n-InP layer 3 is an n-InGaAsP layer 21, which is for improving the response speed degradation caused by the hole pile-up at the hetero-interface, as explained later.
Around the mesa 31 of the n-InP layer 3 is formed an n.sup.- -InP layer 4 for constituting a guard ring region. That is, the mesa of the n-InP layer 3 is embedded in a layer having a relatively low concentration of impurity type. The n.sup.- -InP layer 4 is selectively doped with a p-type impurity together with the doping of the same impurity as in the mesa portion of the n-InP layer 3. Thus, a p-type region, hence, a pn junction, is formed to extend horizontally across the layers 3 and 4.
In FIG. 1, reference 5 denotes a portion in the mesa of n-InP layer 3 converted into p-type material, and dotted line 8 denotes a so-called shallow front of the diffused impurity. This front is a specific property of the diffusion in III-V compound semiconductor single crystals having an impurity of relatively low concentration. Also, AB indicates a multiplication region including the mesa 31 of n-InP layer 3 and GR indicates a guard ring region formed in n.sup.- -InP layer 4.
On the surface of the guard ring region GR is formed an electrode 6 to enclose the surface of the multiplication region AB, while on the back-side surface of the InP substrate 1 is formed another electrode 7. When a reverse bias voltage of a sufficient magnitude is applied between the electrodes 6 and 7 along the direction from the InP substrate 1 to the p-type region 5, the APD can operate in an avalanche multiplication mode.
The APD of FIG. 1 has a separated structure of a light absorption layer (n-InGaAs layer 2) and an avalanche multiplication layer (n-InP layer 3), as proposed by N. Susa, et al., (see "new InGaAs/InP Avalanche Photodiodes Structure for the 1-1.6 .mu.m Wavelength Region", IEEE Journal of Quantum Electronics, QE-16, 864, 1980). This structure is intended to eliminate the tunneling current in the n-InGaAs layer. The tunneling current is due to the relatively narrow band gap (0.75 eV) and small effective mass of the electrons in the n-InGaAs layer, and causes a dark current to reduce the S/N characteristic of the APD.
The APD of FIG. 1 is also formed to to have a structure of the buried n-InP multiplication layer 3 as proposed by K. Yasuda, et al. including some inventors of the present invention, (see "InP/InGaAs Buried-Structure Avalanche Photodiodes", Electronic Letters, Feb. 16, 1984 Vol. 20, No. 4 pp. 158-159). This buried structure features the high-impurity-concentration n-InP multiplication layer 3 buried in the low-impurity-concentration n.sup.- -InP layer 4, thereby providing an enhanced function of the guard ring formed therein. The buried-structure APD is based on a principle that a pn junction formed in a semiconductor having an impurity of relatively low concentration, such as the n.sup.- -InP layer 4, has a higher breakdown voltage compared with that formed in a semiconductor having an impurity of relatively higher concentration, such as n-InP layer 3.
However, in the APD of FIG. 1, the depth from the surface of the device to the pn junction formed across the mesa 31 of n-InP layer 3 and the n.sup.- -InP layer 4 is not equal in the guard ring region GR and the multiplication region AB. There is a general characteristic in semiconductors having the same lattice constant that the lower the carrier concentration or the wider the band gap, the deeper the pn junction formed therein by using impurity diffusion. Accordingly, the pn junction thus formed is nearer to the n-InGaAs light absorbing layer 2 in the n.sup.- -InP layer 4 than in the mesa 31 of the n-InP layer 3. That is, the distance between the pn junction and the InGaAs light absorbing layer 2 is smaller in the guard ring region GR compared with the multiplication region AB, and the effective thickness of the n.sup.- -InP layer 4 is decreased.
In the APD as shown in FIG. 1, the InP substrate 1 is provided with an impurity of high concentration (e.g. on the order of 10.sup.18 cm.sup.-3 compared with 10.sup.15 to 10.sup.16 cm.sup.-3 in the n-InGaAs light absorbing layer 2, n-InP layer 3, etc.), therefore, when an external reverse bias voltage is applied between the electrodes 6 and 7, the depletion layer spreads from the pn junction toward the interface of the n-InGaAs layer 2 and n-InP substrate 1. This means that the electrical field generated in the guard ring region GR is stronger than that formed in the multiplication region AB because of the unevenness between the pn junction in the multiplication region AB and guard ring region GR.
This unevenness between the pn junction in the multiplication region AB and guard ring region GR is probable even when ion implantation or epitaxial growth technology is employed for forming the pn junction because of the accompanying thermal process used to anneal and activate the impurities.
It is important for the design of an APD that the electrical field distribution in the APD must be designed so that the field in the n-InP layer 3, especially in the depletion layer near the pn junction in the mesa 31, must be large enough to cause avalanche multiplication, and the respective electrical fields in the n-InGaAsP layer 21 and n-InGaAs layer 2, in particular, at the respective hetero-interfaces, must be small enough to suppress the tunneling current in the layers. Moreover, the pn junction in the guard ring region is required not to cause breakdown under application of the external reverse bias voltage for producing the avalanche multiplication.
Furthermore, the electrical fields at the respective hetero-interfaces must properly be adjusted to correlate with one another in view of the dark current due to the tunneling electrons and the aforesaid hole pile-up phenomena. If n-InGaAs layer 2 directly intefaces n-InP layer 3, a valence band discontinuity forming a barrier of a height of about 0.4 eV appears. This barrier acts as a trap for the holes generated in the n-InGaAs light absorbing layer 2, and the delayed release of holes from the trap operates to decrease the response speed of the APD. In other words, a certain magnitude of electrical field is required at the hetero-interface between the n-InGaAs layer 2 and n-Inp layer 3 in order to provide the holes with sufficient energy to surmount the barrier. The estimated value for this electrical field is about 3.times.10.sup.5 V/cm or more for an interface made on the (111) A-oriented surface of an InP substrate by using a liquid phase epitaxy (LPE) technique, for example.
However, the electrical field necessary to suppress the tuneling electrons through the n-InGaAs layer 2 must be less than about 2.3.times.10.sup.5 V/cm. These contradictory requirements for the electrical fields can be overcome by introducing an intermediate n-InGaAsP layer 21 which reduces the effective barrier height between the hetero-interface of the n-InGaAs layer 2 and InP layer 3, thereby improving the response speed degradation caused by the hole pile-up at the hetero-interface. (See "InGaAs Avalanche Photodiodes for 1 .mu.m Wavelength Region" Electronics Letters, July 7, 1983, Vol 19, No. 14, pp. 534-536, by T. Shirai, et al. including some inventors of the present invention.) As an equivalent, a so-called transition layer, in which the energy band gap is continuously changed from the 1.35 eV of InP to the 0.75 eV of InGaAs, can be used to substitute for the n-InGaAsP intermediate layer 21.
In the APD of FIG. 1, to suppress the tunneling current and the hole pile-up, the electrical field at the hetero-interface of the n-InGaAsP layer 21 and the n-InP layer 3 must be between 3.5.times.10.sup.5 and 2.5.times.10.sup.5 V/cm, and that at the hetero-interface of the n-InGaAsP layer 21 and n-InGaAs layer 2 must be between 2.3.times.10.sup.5 and 1.5.times.10.sup.5 V/cm, when each of the layers are formed on an (111)A- oriented surface of the InP substrate 1 by using a conventional LPE technique under dissolution free conditions, for example.
These electrical field conditions must be satisfied in both the multiplication region AB and guard ring region GR. However, the difference in the electrical field distributions in the multiplication region and guard ring region due to the unevenness of betwen the pn junction, and the difference in the carrier concentrations of the multiplication region AB and guard ring region GR imposes difficulties on the design, fabrication and operation of the APD.
That is, the degree in latitude of the design parameters of the APD is decreased and severe process controls are imposed to achieve these design parameters. The parameters include, for example, the respective thicknesses of and the impurity concentration in each of the layers 2, 21, 3 and 4 and the diffusion depth of the impurity for creating the pn junction. Moreover, the operational margin of the APD is inevitably reduced. These disadvantages result in the low manufacturing yield and high cost of the APD, and further, limit the practical application possibilities of the APD.